PPA Analysis and Optimization

In the design process of digital chips, Power, Performance, Area (PPA), are the three indicators that designers pay the most attention to. These three indicators are often in a trade-off relationship, and a good design should strike a balance among the three. However, in some special scenarios, we may optimize a certain indicator to meet the specific needs of the scenario, such as pursuing extreme low power consumption on mobile devices and pursuing extreme small area in cost-sensitive links.

Low Power Design

● Multi Voltage Power Supply Technology: two PMICs provide power, and the chip voltage can be adjusted through PMBUS.
● Multi Threshold Voltage Technology: using HVT/RVT/LVT/SLVT, etc
● Clock gating technology: The CRM module has implemented gating for each output clock and integrated automatic insertion gating
● DVFS: Dynamic Voltage Frequency Adjustment.

Performance Analysis

Self developed performance analysis tool for Latency, Bandwidth and Real time critical path.

Physical Design for PPA Optimization

Before Optimization:

The wiring is messy, the device density is not high, the delay is large, and the power consumption is large.

After Optimization:

The line is neat, the distance is short, the delay is small; The device is reasonable, with high density, small area and low power.

Before Optimization:

The wiring is messy, the device density is not high, the delay is large, and the power consumption is large.

After Optimization:

The line is neat, the distance is short, the delay is small; The device is reasonable, with high density, small area and low power.

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Before Optimization:

After Optimization:

Before Optimization:

After Optimization:

Discover how we can streamline your next product design process!

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