Low Power Design
Low Power Design
Low Power Design 01
Low Power Design 02
  • ● Multi Voltage Power Supply Technology: two PMICs provide power, and the chip voltage can be adjusted through PMBUS.
  • ● Multi Threshold Voltage Technology: using HVT/RVT/LVT/SLVT, etc
  • ● Clock gating technology: The CRM module has implemented gating for each output clock and integrated automatic insertion gating
  • ● DVFS: Dynamic Voltage Frequency Adjustment.
Low Power Design 02
Performance Analysis
Performance Analysis
Performance analysis

Self developed performance analysis tool for Latency, Bandwidth and Real time critical path.

Performance analysis

Self developed performance analysis tool for Latency, Bandwidth and Real time critical path.

Physical Design for PPA Optimization
Physical Design for PPA Optimization
Physical Design for PPA Optimization   Before Optimization
Before Optimization:

The wiring is messy, the device density is not high, the delay is large, and the power consumption is large.

After Optimization:

The line is neat, the distance is short, the delay is small; The device is reasonable, with high density, small area and low power.

Physical Design for PPA Optimization   Before Optimization
Before Optimization:

The wiring is messy, the device density is not high, the delay is large, and the power consumption is large.

After Optimization:

The line is neat, the distance is short, the delay is small; The device is reasonable, with high density, small area and low power.

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