One-stop Customized Service for Wireless Chips
One-stop Customized Service for Wireless Chips
Wireless Communication-Block Diagram

High performance and bandwidth Interface IP

  • ● Ethernet CTRL+PHY: Maximum 50/100Gbps
  • ● PCIe Gen5/CXL CTRL+PHY: Maximum 32Gbps per lane
  • ● DDR3/4/5 CTRL+PHY:6.4Gbps
  • ● MCR DDR5 CTRL+PHY:8.8~12.8Gbps
  • ● HBM3e/3/2e CTRL+PHY:9.6Gbps
  • ● INNOLINK/UCIe CTRL+PHY:Maximum 24Gbps

Communication peripheral Interface IP

  • ● JESD 204B: Maximum 12.5Gbps per lane
  • ● JESD 204C: Maximum 32Gbps per lane
  • ● SDIO3.0: Support 1.8/3.3V, up to SDR104

System and Security

  • ● Power consumption and Performance optimization
  • ● CPU Core Selection and Subsystem Design
  • ● Software full SDK delivery
  • ● Secure Boot and Secure Access Design

Product landing

  • ● Product Board and whole Machine design
  • ● Systematic SI/PI simulation and Heat Dissipation design

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