The Innosilicon PCIe4.0 PHY is designed to maximize interface speed in the difficult system environments found in high-performance computing. It is a low-power, area-optimized, silicon-proven IP designed with a system-oriented approach to maximize flexibility and ease integration for our customers. The PCIe4.0 PHY supports PCIe 4.0, 3.0, 2.0 and 1.0 and has full support for manufacturability.

The Innosilicon PCIe4.0 PHY is a high-performance serial link subsystem. Optimized for power in challenging, high-loss channels, our PCIe4.0 PHYs are ideal for networking, storage and data center systems.


  • Available on <14nm
  • Data rate up to 16Gbps/Lane
  • Support 5G/8G/16G different configuration for different protocol applications.
  • 5mW/Gbps per lane
  • Tx EQ and Rx DFE to improve signal integrity.
  • High-speed / Low Jitter PLL as clock source
  • IO Pad / ESD structure embed
  • BIST logic integrated with PRBS pattern
  • 0.8V / 1.8V power supply



  • Higher Bandwidth upto 64Gbps in X4 mode
  • Support different configuration for different protocol applications
  • Lowest power consumption per Gbps data rates


  • Enterprise computing
  • Storage networks
  • Automotive
  • GPU interfacing
  • Server connectivity
  • Network-on-Chip (NoC)
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