The Innosilicon 56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. The PHY has been configured to support a wide range of HS SERDES protocols, including 56G PAM-4 and NRZ, through changes to the PCS layer and register settings.
The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.
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The PHY is fully compliant with the following standards: