The Innosilicon 56G SERDES PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. The PHY has been configured to support a wide range of HS SERDES protocols, including 56G PAM-4 and NRZ, through changes to the PCS layer and register settings.

The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach Serdes solution meets the functionality, power, performance and area requirements of a variety of network applications.

Contact us to learn more about our 56G SerDes IP.



  • 56Gbps serial data speed, supports IEEE 802.3 and OIF standards electrical specifications.
  • Support 28-32G VSR/SR/MR/LR NRZ and 56G PAM-4.
  • Support up to -36dB+ insertion loss @14GHz.
  • Reference clock: 100/156.25MHz from external or through on-chip
  • Embedded high precision low jitter LC PLL and CDR loop.
  • 85-ohm differential on-chip terminated drivers and receivers with automatic impedance calibration.
  • Multiple Built-in self-test modes and test pattern generation.
  • Near-end serial loopback for testability.
  • Far-end parallel loopback for testability.
  • Proprietary low cap ESD structures.
  • On-chip PRBS generation and verification controlled from external terminal.
  • Well-tuned IO and PKG model to achieve good SI and performance.


The PHY is fully compliant with the following standards:

  • PCIE6/5
  • IEEE 802.3 and OIF
  • CEI-56G+ LR PAM-4
  • CEI-25G+ LR/MR NRZ
  • JESD204C/B (25/32G)
  • 10GKR/100G KR-4 LR
  • 400GAUI-8 LR/MR
  • CEI11G-LR

Test Eye-diagram & Jitter Histogram (56Gbps):


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