The Innosilicon 32G SerDes PHY is a highly configurable IP solution capable of supporting data rates of up to 32 Gbps per lane. It is designed to accommodate a wide range of high-speed SerDes protocols, including PCIe, USB, Rapid IO, XAUI, SATA, Ethernet, and JESD204B/C, through flexible PCS layer configurations and programmable register settings. The PHY is architected to support multi-lane implementations, featuring a shared common block that integrates a Tx PLL, reference clock input, bandgap, bias circuitry, and termination calibration. This common block efficiently supports up to four Tx/Rx lanes, enabling scalable and high-performance connectivity solutions.