32G Multi-SerDes PHY
32G Multi-SerDes PHY
The PHY is physically configured in order to support multi-lane solutions. There is a common block with TX PLL, reference clock input, bandgap, bias circuitry, and termination calibration. This common block can then support up to 4 lanes of TX/RX.

The PHY is fully compliant with the following standards: HMC-32G25G/12.5G -VSR/SR/MR, PCI Express 5.0/4.0/3.0, USB3.1/3.0, FC Serdes, RapidIO3.1/2.x/1.x, CPRI 5.0, XAUI:10GBASE-KX-4/RXAUI, SGMII/10G KR/100G KR-4, SATA3.0/SAS3.0, CEI-6G SR/CEI-11G SR/CEI-32G VSR/MR, JESD204B/204C, Customized SerDes.
Test Eye-diagram & Jitter Histogram (32Gbps)
Test Eye-diagram & Jitter Histogram (32Gbps)
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Offers leading performance, power, and area per terabit
  • Optional PI/SI and thermal co-design service
  • Full support from IP delivery to production
    Reference Clock
  • 19.2-300MHz, integer multiple of Serial output (100MHz for PCIe)
  • +/-300ppm frequency stability (<20Gbps)
  • +/-100ppm frequency stability (>=20Gbps)
  • Supports both SRNS & SRIS modes
  • Configurable as reference clock repeater
  • Internal PLL
  • Used to drive all PHY transmitters and receivers
  • LC-tank architecture operational from 16-32 Gbps
  • Ring PLL covering 1.0-16Gbps
  • Programmable pre-divider & feedback divider
  • Initiative SSC or reference clock based passive SSC
  • LOCK indication
  • Data Transmit
  • Rates supported from 1.0-32 Gbps
  • AC coupled
  • 50Ω impedance, internally calibrated
  • 200-1100mV differential peak-peak, programmable
  • 3 tap pre/post-cursor de-emphasis, programmable
  • Programmable Rise/Fall times
  • Data Receive
  • AC coupled
  • 50Ω impedance, internally calibrated
  • 200-1200mV differential peak-peak
  • CTLE, programmable
  • DFE, 6-tap programmable
  • CDR
  • Testing
  • Scan
  • BIST with PRBS7, PRBS23 and PRBS31(PG & SD)
  • Loopback (near-end , far-end, on/off-die)
  • On-chip scope (eye height & width)
  • Analog and digital probe points
  • HTOL
  • IDDQ
  • ESD
  • HBM 2000V, [JEDEC JS-001-2014]
  • MM 100V, [JEDEC JESD22-A115C]
  • CDM 250V, [JEDEC JESD22-C101F]
  • Latch Up
  • +-200mA for IO and 1.5*Vsupply for power rails
  • Package
  • Wire bond with careful SI/PI analysis for 8Gbps and below
  • Flip-Chip with careful SI/PI analysis for 8Gbps and up
  • Interface with controller
  • PIPE4.3 & 32 bits data bus for PCIe and USB3.x
  • SAPIs for SATA3.0
  • UTMI+ (level3) 8/16bit for USB2.0 (as a separated IP not described in this document)
  • XGMII for XAUI and 10GbE
  • SerDes interface for customized PCS
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation

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