The INNOSILICON MIPI D-PHY is compliant with V1.2 spec and can combine either a high-speed transmitter or receiver with a low speed transceiver to support ULP, LP and HS operation. The D-PHY uses the standard PPI digital interface to simplify controller integration and supports CSI, DSI and UniPro MIPI protocols. An optional CSI controller is available.
The architecture is customizable and supports 1 to 4 lanes for increased throughput. Some of the more common customizations we have provided in the past include:
Designed with ease of integration in mind. The PHY is small, low power and contains all I/Os along with primary and secondary ESD.
Efficient production testing is assured through built-in BIST, loop back and Boundary scan support.
SMIC 28PS, GF 28SLP
SMIC 55LL, GF 55LPX
SMIC 90G, SMIC 90LL
SMIC 110G, TSMC 110G
SMIC 130G, TSMC 130G
MIPI TTL/LVDS combo:
SMIC 28PS, GF 28SLP, TSMC 28HPC