56G SerDes

The Innosilicon 56G SerDes PHY is a highly configurable PHY capable of supporting speeds up to 56Gbps within a single lane. For this datasheet, the PHY has been configured to support 56G PAM-4 and NRZ specifically, but the PHY itself can be configured to support a wide range of HS SERDES protocols through changes to the PCS layer and register settings.

56G SerDes

The hard-macro PHY is well-architected for IEEE and OIF protocols, with ESD structure and BIST function accommodated. This IP powers high-speed interconnectivity between chips, optics and, backplanes with the built-in low-jitter LC PLL and CDR to optimize the signal integrity. The Innosilicon 56G Long Reach SerDes solution meets the functionality, power, performance, and area requirements for a variety of network applications.

The PHY is fully compliant with the following standards: PCIE6/5, IEEE 802.3 and OIF, CEI-56G+ LR PAM-4, CEI-25G+ LR/MR NRZ, JESD204C/B (25/32G), 10GKR/100G KR-4 LR, 400GAUI-8 LR/MR, CEI11G-LR.

Test Eye-diagram & Jitter Histogram （56Gbps）

Highlights
Features
Standard Deliverables
Example Applications

Offers leading performance, power, and area per terabit
Optional PI/SI and thermal co-design service
Full support from IP delivery to production

64/56Gbps serial data speed, supports IEEE 802.3 and OIF standards and electrical specifications
Supports 28-32G VSR/SR/MR/LR NRZ and 64/56G PAM-4
Supports up to -36dB+ insertion loss @14GHz
Reference clock: 100/156.25MHz from external or through on-chip
Embedded high precision low jitter LC PLL and CDR loop
85-ohm differential on-chip terminated drivers and receivers with automatic impedance calibration
Multiple Built-in self-test modes and test pattern generation
Near-end serial loopback for testability
Far-end parallel loopback for testability
Proprietary low cap ESD structures
On-chip PRBS generation and verification controlled from an external terminal
Well-tuned IO and PKG model to achieve good SI and performance

Databook and detailed physical implementation guides
Complete set of timing models
Library Exchange Format (LEF)
Encrypted Verilog Models
Layout vs. Schematic (LVS) report
GDSII database

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