DDR3/4/LPDDR3/4/4X Combo PHY & Controller
DDR3/4/LPDDR3/4/4X Combo
PHY & Controller
Note that all Innosilicon PHYs are pre-assembled with.lib, LEF, and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 8 bit to 72 bit or more. Innosilicon is happy to pre-assemble each PHY for our customer so that integration is extremely easy.

The combo PHY solution includes DDRn controller and PHY, supporting DDR3/4/LPDDR3/4/4X. From configurable timing and driving strength parameters to interface and the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market,
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
  • Up to DFI4.0 compliant memory controller interface
  • Flexible pad ring configuration to adapt for various design and chip scenarios
  • Integration with other Innosilicon interface IP
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed
    DDRn/LPDDRn Combo PHY supports the following features:
  • Compliant with JESD79-3 DDR3 specifications, up to 2133Mpbs
  • Compliant with JESD79-4 DDR4 specifications, up to 3200Mpbs
  • Compliant with JESD209-3 LPDDR3 specifications, up to 2133Mbps
  • Compliant with JESD209-4 LPDDR4/4X specifications, up to 4266Mbps
  • Compliant with DFI 4.0 Specifications
  • Supports max to 4 DRAM ranks
  • Supports DQ width: max to 72bit for DDR3/4 and 64 bit for LPDDR3/4
  • Multiple drive and ODT strengths adjustable
  • Supports per-bit De-skew tuning for Command
  • Supports per-bit De-skew tuning for Data
  • Supports CMD map
  • Supports Data BIT(not cross Byte) Map
  • Supports Command Bus Training (Only support LPDDR4/4x)
  • Supports Command/Data IO Driver Strength adjustment
  • Automatic RX DQS Training/Bypass RX DQS Control
  • Automatic Write Leveling Training/Bypass Write Leveling Control
  • Automatic Read Training
  • Supports MPR/MPC pattern training mode

  • Automatic Write Training (Only supports predefined pattern training mode)
  • Bypass Write Training/Read Training
  • Voltage and Temperature Compensation for RX Path
  • PVT Compensation and timing calibration for all corner reliability
  • Supports ZQ calibration
  • Various low Power Control of the PHY
  • Power down low power mode

    Stop clock low power mode

    DFI Low Power Interface low power mode

  • Supports Built-In Self-Test
  • Supports Boundary Scan of pad
  • Supports stuck-at or At-speed scan scan chain
  • Supports fast frequency change up to 4 points
  • Apb 2.0/3.0/4/0 interfaces to configure registers for different interfaces
  • Supports both wire-bond and flip- chip packaging
  • Wire-bond speed is package limited (no comma, make supporting bullet point)

  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation
  • Documentation for the Innosilicon PHY will be delivered as part of the access package.

  • SDC reference File
  • Simulation environment, user guide and test guide
Use Cases for DDR4/3

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