MCR DDR5/DDR5/DDR4 PHY & Controller
MCR DDR5/DDR5/DDR4
PHY & Controller
The Innosilicon system-aware design methodology used for IP Cores delivers a customer focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization and debug.
MCR DDR5 6.4Gbps X2 Ready in Q3/24
MCR DDR5 6.4Gbps X 2 Ready in Q3/24
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • DFI5.0 compliant memory controller interface
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed
  • Support MCR DDR5 MRDIMMs, standard DDR5/4 LRDIMMs/RDIMMs/UDIMMs and standard DDR5/4 signaling, rates from 20Mbps up to 9600Mbps (MCR DDR5)
  • x16/x32/x64/x72/x80 data path interface extendable, support both MCR and standard DDR5/4 DIMMs, or standard DDR5/4 SDRAM devices.
  • 1.2V(DDR4)/1.1V(DDR5) JEDEC IO standard, supporting 1.2V POD_12/1.1V POD_11 I/Os
  • Support DDR5 dual channel mode, dual 32bit data +8bit ECC
  • Support CA training, CS training, and write leveling training modes
  • Support Write FFE and Read DFE equalization
  • Independent read and write timing adjustments with auto calibration, dynamic V&T tracking
  • Both Read and Write Per bit de-skew support
  • Support over 10 training modes for stability working
  • Support Maximum 4 frequency points fast change
  • Supports point to point memory sub systems and multi-rank
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power including self-refresh support
  • APB Port register access interface
  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation
  • Documentation for the Innosilicon PHY will be delivered as part of the access package.

  • Verilog Getech File
  • SDC File
  • Simulation environment and user guide
Use Cases for DDR5/4

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