Master/Slave DLL
Master/Slave DLL
The DLL PHY components contain DLL specialized for utility and functionality up to 800Mbps in UMC 28nm, critical timing synchronization module (TSM), and low power/jitter DLLs with programmable fine-grain control for any DLL application.
DLL Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Power consumption
  • Fully customizable
  • High speed hub use VLPI low latency
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Reference clock frequency range from 200MHz to 800MHz
  • Output clock phase:0/90/180/270
  • Cycle to Cycle jitter(C2C): ≤150ps
  • GDSII
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines
Use Cases for DLL

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