Master/Slave DLL
Master/Slave DLL
The DLL PHY is designed to generate precise phase-shifted clocks (e.g. 0 ° , 90 ° , 180 °, 270 °) based on a reference clock, enabling high-speed data capture and transmission. It consists of the Master DLL and Slave DLL, each serving specific roles in the clock distribution network.
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Low power consumption
  • Fully customizable
  • High speed hub using VLPI low latency
  • Small area
  • Simple integration process
  • Reference clock frequency range from 200MHz to 800MHz
  • Generates accurate phase-shifted clocks (e.g., 0/90/180/270) synchronized with the reference clock
  • Optimized for low-power operation
  • Ensures proper alignment for high-speed data sampling and transmission
  • Provides stable and reliable clock alignment
  • Allows customization of delay settings, phase shifts and other parameters to meet specific application requirements
  • Designed to mitigate the effects of noise and jitter
  • Cycle to Cycle jitter (C2C): ≤150ps
  • GDSII
  • LVS Spice netlist
  • Verilog model
  • Synopsys synthesis model
  • LEF for clock generator PLL
  • User Guidelines
Use Cases for DLL

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