GDDR6X/6 PHY & Controller

Innosilicon GDDR6X/6 Combo PHY is fully compliant to the JEDEC GDDR6X/6 standard, supporting up to 20Gbps per pin for NRZ GDDR6 and 24Gbps for PAM4 GDDR6X. The GDDR6/6X interface supports 2 channels, each with 16 bits for a total data width of 32 bits per memory device. With speeds up to 20 Gbps/24Gbps per pin, the Innosilicon GDDR6/6X PHY will offer a maximum bandwidth of up to 80Gbps or 96Gbps per memory device. This PHY is available in advanced FinFET nodes for leading-edge customer integration.

The Innosilicon system-aware design methodology used for IP Cores delivers a customer-focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization, and debugging.

GDDR6-20Gbps NRZ

GDDR6X-24Gbps PAM4

Highlights
Features
Standard Deliverables
Example Applications

High bandwidth, Process Friendly（14/12nm down to 3nm）
GDDR6/6X combo PHY & controller in Mature High Volume
Package & PCB services, Supports GDDR6/6X up to 24Gbps
From A to Z Support: IP integration, Packaging/Testing, system optimization and production support

Combo for GDDR6 with data rate up to 20Gbps (GDDR6) and 24Gbps (GDDR6X)
Pseudo open drain (POD‐135) compatible outputs
Driver strength and ODT auto calibration
PHY independent auto Command Address Training
PHY independent software Command Address Training
PHY independent auto WCK2CK Training
PHY independent auto Read Training
PHY independent software Read Training
PHY independent RX Vref Training
PHY independent auto Write Training
PHY independent software Write Training
Supports WDBI/RDBI/CABI functions
Supports EDC QDR/DDR modes
Rx DFE for data inputs, with receiver characteristics programmable per pin
Supports both Write and Read CRC
Per bit Tx and Rx data phase delay and VREF adjustment
Internal high performance low jitter PLL
Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
Supports both Quad data rate (QDR) and double data rate (DDR) data (WCK) modes
Supports dynamic Read Training/Write Training with auto-refresh synchronize function
Supports accommodate Voltage/Temperature timing drift
Supports independent TX/RX/CMD delay line
Supports FR4 PCB material
Optional package/PCB design and SIPI analysis service
Supports Micron, Samsung, Hynix memory devices

LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation

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