GDDR7 PHY & Controller

Innosilicon GDDR7 PHY is fully compliant with the JEDEC GDDR7 standard, supporting up to 32Gbps for PAM3 GDDR7. In PAM3 mode, the byte consists of ten DQ and one DQE signals, and the GDDR7 also supports the NRZ IO signaling mode for low power operation. With speeds up to 32Gbps per pin, the Innosilicon GDDR7 PHY will offer a maximum bandwidth of up to 128Gbps per memory device. This PHY is available in advanced FinFET nodes for leading-edge customer integration.

GDDR7
PHY & Controller

The Innosilicon system-aware design methodology used for IP Cores delivers a customer-focused experience with improved time-to-market and first-time-right quality. Innosilicon offers flexible delivery of IP cores and will work directly with the customer to provide a full system signal and power integrity analysis, creating an optimized chip layout. In the end, the customer receives a hard macro solution with a full suite of test software for quick turn-on, characterization, and debugging.

Highlights
Features
Standard Deliverables
Example Applications

Our GDDR7 IP is design ready and will be silicon validated by Q3 2024
High bandwidth, Process Friendly（14/12nm down to 3nm）
Package & PCB services, Supports GDDR7 up to 32Gbps
From A to Z Support: IP integration, Packaging/Testing, System optimization, and Production Supports

GDDR7 with data rate up to 32Gbps
Combo for GDDR6 with data rate up to 20Gbps
Supports for PAM3/NRZ compatible
Driver strength and ODT auto calibration
PHY independent auto Command Address Training
PHY independent software Command Address Training
PHY independent auto ERR Training
PHY independent auto Read Training
PHY independent software Read Training
PHY independent RX VREF Training
PHY independent auto Write Training
PHY independent software Write Training
Supports training pattern by custom and LFSR
Supports RCK Single or differential end
Supports ERR signal communicating function
Supports Burst length: 16 Symbols (PAM3) or 32 (NRZ)
Supports read/write CRC,CA parity
Programmable READ and WRITE latency
Supports per bit TX and RX data phase adjustment
Internal high-performance low jitter PLL
Supports temperature Controlled Self Refresh rate
Supports on-die ECC with error severity reporting during Reads
Supports dynamic Read Training/Write training with auto-refresh synchronize function
Accommodates Voltage/Temperature timing drift
Supports 4-channel/2-channel mode configuration
Rx DFE for data inputs, with receiver characteristics programmable per pin
Tx de-emphasis EQ and Rx DFE EQ to improve signal integrity
Supports independent TX/RX/CMD delay line
Supports FR4 PCB material
Optional package/PCB design and SIPI analysis service

LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation

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