HBM3E/4 PHY & Controller

The third and fourth-generation HBM (HBM3E/4) technology is outlined by the JESD238 standard, 256 bit prefetch per memory read and write access, 1024-bit input/output for HBM3E, 2048-bit input/output for HBM4, and 0.4 V I/O voltages. Just like its predecessor, HBM3E/4 supports two, four, eight, twelve, or sixteen DRAM devices on a base logic die (2Hi, 4Hi, 8Hi, 12Hi，16Hi stacks) per KGSD. HBM Gen 3 expands the capacity of DRAM devices within a stack to 48GB and increases the data rate by up to 9.6Gbps per pin. In addition, the new technology brings an important improvement to bandwidth maximization.

The Innosilicon HBM3E/4 is part of Innosilicon’s broad leading-edge memory IP portfolio that includes GDDR7/6/6X and DDR5/LPDDR5X. Developed by our experienced team with great expertise, the Innosilicon product family enables customers to achieve the best design results while accelerating the time to market.

HBM3E 8.4Gbps on die scope

HBM4 10Gbps

Structure Chart

Highlights
Features
Standard Deliverables
Example Applications

Silicon validated PHY+Controller Complete Solution
HBM3E/4 up to 10Gbps, HBM2E 3600Mbps
From A to Z support: IP integration, 2.5D, Interposer design and simulation, package design and simulation, production tests, complete supply chain

Compliant with JEDEC Specification, up to 10Gbps
Compliant with DFI 3.1 Specifications (dfi_clk_1x : WDQS = 1:4)
Supports up to 16 channels with 64 DQ-width + Optional DBI/ECC/SEV pin support/channel for HBM3E
Supports up to 32 channels with 64 DQ-width + Optional DBI/ECC/SEV pin support/channel for HBM4
Supports command and DQ parity
Supports per-AWORD de-skew tuning for command
Supports bit-group de-skew tuning for data
Supports CMD lane repair
Supports DQ lane repair
Supports automatic and soft command bus training
Supports command and data IO driver strength adjustment
Supports automatic and soft RX DQS training and bypass RX DQS control
Supports automatic and soft WDQS2CK training and bypass WDQS2CK Control
Supports automatic and soft read training
Supports automatic and soft write training
Supports bypass write and read trainings
Supports automatic retraining mode and retraining bypass mode
Supports ZQ calibration
Supports Built-In Self-Test
Supports boundary scan of pad
Supports scan chain
APB 3.0 interfaces to configure registers
Supports IEEE1500 port for direct access to the memory stack and PHY using APB
Supports HBM DRAM initialized by PHY

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist for I/Os
Databook, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation

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