HBM4/3E PHY & Controller
The fourth-generation and third-generation HBM (HBM4/3E)
technology is outlined by the JESD238A standard (for HBM3E) and an
upcoming specification (for HBM4). These technologies feature
256-bit memory access per channel, with a 1024-bit input/output
interface for HBM3E and up to a 2048-bit interface for HBM4. The
I/O voltage is 0.4 V for HBM3E, while HBM4 further reduces this.
Similar to previous generations, HBM4/3E supports two, four,
eight, twelve, or sixteen DRAM devices on a base logic die (2Hi,
4Hi, 8Hi, 12Hi, 16Hi stacks) per KGD. HBM3E expands the capacity
of DRAM devices within a stack to 48GB, and increases the data
rate to up to 9.6Gbps per pin.
