LPDDR5/5X/4/4X
Combo PHY & Controller
LPDDR5/5X/4/4X
Combo PHY & Controller
All INNOSILICON PHY is pre-assembled with.lib, LEF and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 8 bit to 64 bit or more. INNOSILICON is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.

The combo PHY solution includes DDRn controller and PHY, supporting LPDDR5/5x/4/4x. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.
LPDDR5T 9600Mbps Test Eye Diagram
LPDDR5T 9600Mbps Test Eye Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Fully pre-assemble design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • DFI4.0/4.1/5.0 compliant memory controller interface
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed
  • LPDDR5/5x and LPDDR4/4x modes & signaling, rates from 20Mbps up to 9600Mbps (LPDDR5x), 6400Mbps (LPDDR5) and 4266Mbps (LPDDR4/4x), respectively
  • x16/x32/x64 data path interface extendable
  • Support JEDEC LPDDR4/4x 1.1V/0.6V and LPDDR5 0.5V/0.3V LVSTL IO voltage
  • Support LPDDR5 WCK mode, Data copy, Write X and Link ECC features
  • Independent read and write timing adjustments with auto calibration
  • Programmable write post-amble (0.5 tCK or 1.5 tCK)
  • Support both PoP and discrete memory package
  • Support silicon signal and PG bumps customized to optimal package design.
  • Support various low power mode, support DFS and retention mode
  • Support point to point memory sub systems and multi-rank
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion, PAD and internal loop back modes
  • Various power-down modes for low power including self-refresh support
  • Low jitter with superior noise rejection
  • APB Port register access interface
  • Implemented using RVT&LVT&ULVT core devices and standard technology IO devices
  • Support both wire-bond and flip- chip packaging
  • Wire-bond speed is package limited
  • Support different DDRn type signal mapping for feasible PCB layout
  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist or IBIS model for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation
  • Documentation for the Innosilicon PHY will be delivered as part of the access package.

Use Cases for LPDDR5/5X/4/4X

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