LPDDR5/5X/4/4X PHY & Controller

The Innosilicon DDR IPTM Mixed-Signal LPDDR5/5x/4/4x COMBO PHYs provide turnkey physical interface solutions for ICs requiring access to JEDEC compatible SDRAM devices. It is optimized for low power and high speed applications with robust timing and small silicon area. It supports all JEDEC LPDDR5/5x/4/4x SDRAM components in the market. The PHY components contain DDR specialized functional and utility high performance I/Os, critical timing synchronization modules (TSM), and a low power/jitter DLLs with programmable fine-grain control for any SDRAM interface.

LPDDR5/5X/4/4X
Combo PHY & Controller

All Innosilicon PHY is pre-assembled with.lib, LEF, and GDS so that it is very easy to integrate the PHY with any existing SoC floor plan. DDRn bus width can be from 8 bit to 64 bit or more. Innosilicon is happy to pre-assemble each PHY for our customer so that integration becomes extremely easy.

The combo PHY solution includes the DDRn controller and PHY, supporting LPDDR5/5x/4/4x. With configurable timing and driving strength parameters to interface to the wide variety of SDRAMs, the PHY is very flexible with advanced command capability to increase SDRAM operation efficiency.

LPDDR5T 9600Mbps Test Eye Diagram

Highlights
Features
Standard Deliverables
Example Applications

Fully pre-assembled design, Drop-in hard macro to ease integration and speed up time to market
Zero risk with robust ESD architecture
Maintains self-refresh I/O drive state during VDD power down
Extensive EDA tool support for various design automation flows
DFI4.0/4.1/5.0 compliant memory controller interface
Takes full advantage of process power savings and speed capability
Best in class low noise design to ensure best timing margin and signal integrity
DFT functions to reduce test time and ensure high test coverage
Several programmable PHY operating modes through simple register interface
Per Bit De-skew to improve composite data eye during read cycles at high speeds

LPDDR5/5x and LPDDR4/4x modes & signaling, rates from 20Mbps up to 9600Mbps (LPDDR5x), 6400Mbps (LPDDR5) and 4266Mbps (LPDDR4/4x), respectively
x16/x32/x64 data path interface extendable
Supports JEDEC LPDDR4/4x 1.1V/0.6V and LPDDR5 0.5V/0.3V LVSTL IO voltage
Supports LPDDR5 WCK mode, Data copy, Write X and Link ECC features
Independent read and write timing adjustments with auto calibration
Programmable write post-amble (0.5 tCK or 1.5 tCK)
Suppors both PoP and discrete memory package
Supports silicon signal and PG bumps customized to optimize package design.
Supports various low power modes, support DFS and retention modes
Supports point to point memory sub systems and multi-rank
PVT compensation and timing calibration for all corner reliability
At speed BIST, scan insertion, PAD and internal loopback modes
Various power-down modes for low power including self-refresh support
Low jitter with superior noise rejection
APB Port register access interface
Implemented using RVT&LVT&ULVT core devices and standard technology IO devices
Supports both wire-bond and flip-chip packaging
Wire-bond speed is package limited
Supports different DDRn type signal mappings for feasible PCB layout

Verilog models
LEF
Place-and-route abstracts
GDSII files
LVS netlists
Optional extracted HSPICE netlist or IBIS model for I/Os
Data book, Application notes
Silicon validation and ESD testing results
Optional PCB reference design and Package Electrical Model
Documentation

Documentation for the Innosilicon PHY will be delivered as part of the access package.

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