LVDS TX and RX PHY
LVDS TX and RX PHY
Innosilicon LVDS TX PHY contains four 7-bit parallel-load serial-out shift registers, a 7x clock PLL, and five LVDS line drivers in a single integrated circuit. Innosilicon LVDS RX PHY contains serial-to-parallel logic and PLL. Both LVDS TX PHY and LVDS RX PHY contain register banks, which can be configured by registers through APB bus. In addition, both Innosilicon LVDS TX PHY and Innosilicon LVDS RX PHY can be extended from 5 lanes to n lanes (n value is provided by the customer). Therefore, the TTL lines extend respectively.
LVDS/TTL Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Fully customizable
  • High speed hub use VLPI low latency
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Meet or exceeds the requirements of 900mV/1200mV Vcom sub-LVDS standard
  • The IP supports the full specifications described in LVDS IEEE Std1596.3-1996
  • Supports byte clock mode and DDR clock mode
  • Supports data rates up to 1.2Gbps bandwidth per lane
  • 200Mbps maximum data transfer rate per pad on TTL mode
  • Embedded PLL supporting integer and fractional modes
  • Supports built-in BIST test mode
  • Supports 1 clock lane and extensible data lanes
  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)
Use Cases for LVDS/TTL

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