MIPI C/D-PHY

The D-PHY and C-PHY support the electrical portion of MIPI D-PHY V2.0 standard and MIPI C-PHY V1.1 standard, covering all transmission modes (ULP/LP/HS). This IP cost-effectively adds MIPI D-PHY and MIPI C-PHY capability to any SoC used in communication and consumer electronics fields.

MIPI C/D-PHY

MIPI C/D-PHY CSI/DSI TX and RX

Innosilicon CSI-2Controller implements MIPI CSI-2 V1.3 protocols. The CSI-2 link protocol specification is a part of a group of communication protocols defined by MIPI Alliance standards intended for mobile system chip to chip communications. The CSI-2 specification specially targets Camera to Image application processor communication.

Innosilicon DSI-2 Controller implements MIPI DSI-2 V1.0 protocols. The DSI-2 link protocol specification is a part of a group of communication protocols defined by MIPI® Alliance, which is intended for mobile system chip to chip communications. The MIPI DSI specification targets display communications in image application processors.

The Innosilicon I/O and ESD are also built-in together in a rectangular footprint for any configuration. It is optimized for high-speed applications with robust timing and small silicon area.

Highlights
Features
Standard Deliverables
Example Applications

Low power consumption
Fully customizable
High speed hub use VLPI low latency
Small area
Simple integration process
Available options include

Test chips and test boards

FPGA integration support

Chip level integration

Compliant with MIPI® Alliance Specification for D-PHY V2.0
Compliant with MIPI® Alliance Specification for C-PHY V1.1
Compliant with MIPI® Alliance Specification for DSI-2 V1.0
Compliant with MIPI® Alliance Specification for CSI-2 V1.3
HS, LP, ULPS modes supported
4.5Gbps maximum data transfer rate per lane on D-PHY mode
3.5Gsps maximum data transfer rate per trio on C-PHY mode
Asynchronous transfer at low power mode with a bit rate of 10Mbps on both C-PHY and D-PHY
Unidirectional and bi-directional modes supported
Skew-calibration for D-PHY supported
ECC and CRC insertion supported
Automatic termination control for HS and LP modes
Buffers with tunable on-die-termination and advanced equalization
Supports BIST logic
Supports combo LVDS/TTL IP
Supports combined with DSC1.2A for delivery

Databook and physical implementation guides Netlist (Spice format for LVS)
Library Exchange Format (LEF)
Verilog Models
GDSII to Foundry IP Merge
Module integration guidelines
Silicon validation report (when available)
Evaluation board (when available)

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