MIPI M-PHY
MIPI M-PHY
Innosilicon M-PHY includes transmitters and receivers to implement full-duplex operations. The IP supports multiple BURST modes, including HS and LS for improved power efficiency and multiple power saving modes where power consumption can be traded-off for recovery time.

The Innosilicon I/O and ESD are also built-in, providing a convenient, drop-in PHY. The design is optimized for high speed applications with robust timing and small silicon area.

The Innosilicon M-PHY supports the electrical portion of MIPI M-PHY V3.0 standard and cost-effectively adds MIPI M-PHY V3.0 capability to any SOC.
MIPI M-PHY Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Fully customizable
  • High speed hub use VLPI low latency
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Compliant with MIPI Alliance Standard for MIPI M-PHY V3.0 Specifications
  • Supports standard RMMI interface for UniPro™(UFS2.1,CSI-2,DSI-3), SSIC, LLI
  • Supports 2 lanes in M-TX and 2 lanes in M-RX sub-links
  • Supports HS Mode (GEAR1~3, A/B)
  • Supports LS Mode (PWM G0~G3)
  • Supports data rates up to 5.8304Gbps per lane
  • Supports M-PHY Type-I, Type-II
  • Supports reference clock frequencies: 19.2/26/38.4/52MHz
  • Supports LS-BURST, HS-BURST, STALL, SLEEP, HIBERN8 states
  • Dynamic configuration and control via core ports
  • Databook and physical implementation guides Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • Silicon validation report (when available)
  • Evaluation board (when available)
Use Cases for MIPI M-PHY

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