ONFI PHY & Controller
PHY & Controller
The Innosilicon AXI interface ONFI Controller (hereinafter referred to as “Controller”) provides four AXI channels to connect to the Innosilicon ONFI PHY, which is compliant with the specifications of DFI digital interfaces.

This Controller uses two-layer architecture which makes the interface flexible and easy to be converted to the desired multi-port bus format and timing sequence. One layer is the CPU bus core with the ability to host a single or a multiport CPU bus; the other layer is the controller core to communicate with the DFI PHY. Between the two layers the TX/RX data FIFO, a generic command FIFO, is utilized to make the internal controller immune to the changes of the CPU bus core.

The overall design of the Controller is versatile, light-weight, and easily adjustable to the CPU bus ports. It has high efficiency yet not overly large gate counts. All interface timing on DFI and controller are in 1x SDR clock domain which can be half of the speed of the PHY core. The interface is fairly generic and supports high-performance input and output data flow, reaching up to 4800Mbps ONFI speeds in a wide range.
ONFI Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Fully pre-assembled design, Drop-in hard macro for easy integration and quick time to market,
  • Zero risk with robust ESD architecture
  • Maintains CE I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • Flexible pad ring configuration to adapt for various design and chip scenarios
  • Integration with other Innosilicon interface IP
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed
  • ONFI5.1 modes & signaling, rates up to 4800Mbps
  • x8/x16 data path interface extendable
  • Supports 1.2 V/1.8V I/Os
  • Multiple drive strengths adjustable
  • Independent DCC training, Vref training for NV-DDR3/NV-LPDDR4
  • Independent read and write timing adjustments with auto calibration for NV-DDR3/NV-LPDDR4
  • Low latency with programmable timings for secure data handling
  • Per bit deskew support
  • Supports point to point memory subsystems, multi-host, and multi-channel
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power
  • Low jitter with superior noise rejection
  • APB Port register access interface
  • Supports both wire-bond and flip- chip packaging
  • Wire-bond speed is package limited
  • Supports different signal mappings for feasible PCB layout
  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE or ibis model for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation
  • Documentation for the Innosilicon PHY will be delivered as part of the access package.

  • SDC reference File
  • Simulation environment and user guide
Use Cases for ONFI

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