The Innosilicon AXI interface ONFI Controller (hereinafter referred to as “Controller”) provides four AXI channels to connect to the Innosilicon ONFI PHY, which is compliant with the specifications of DFI digital interfaces.

This Controller uses two-layer architecture which makes the interface flexible and easy to be converted to the desired multi-port bus format and timing sequence. One layer is the CPU bus core with the ability to host a single or a multiport CPU bus; the other layer is the controller core to communicate with the DFI PHY. Between the two layers the TX/RX data FIFO, a generic command FIFO, is utilized to make the internal controller immune to the changes of the CPU bus core.

The overall design of the Controller is versatile, light-weight, and easily adjustable to the CPU bus ports. It has high efficiency yet not overly large gate counts. All interface timing on DFI and controller are in 1x SDR clock domain which can be half of the speed of the PHY core. The interface is fairly generic and supports high-performance input and output data flow, reaching up to 4800Mbps ONFI speeds in a wide range.