PCIe 5.0/4.0/3.0

The Innosilicon PCIe5.0/4.0/3.0 IP solutions consist of controllers and PHYs. The solutions are designed to support PCIe5.0, PCIe4.0, PCIe3.1, PCIe2.1, PCIe1.1 specification, and PIPE specification. The Innosilicon PCIe IP solutions provide high performance, low latency, and rich flexibility for enterprise computing, storage networks, automotive, and I/O connectivity application.

PCIe 5.0/4.0/3.0

PCle5.0/4.0/3.0 PHY & Controller

PCle5.0/4.0/3.0
PHY & Controller

The Innosilicon PCle5.0/4.0/3.0 PHY is a highly configurable PHY capable of supporting speeds up to 32Gbps within a single lane. For this particular datasheet, the PHY has been configured to support PCle5.0/4.0/3.0 specifically, but the PHY itself can be configured to support a wide range of HS SerDes protocols through changes to the PCS layer and register settings.

The lnnosilicon Gen1/2/3/4/5 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It's a high performance, high reliability, low latency, low area, low power, and easy to integrate PCI Express solution. This Controller supports up to x16 Gen1 (2.5Gb/s), Gen2 (5.0Gb/s), Gen3 (8.0Gb/s), Gen4 (16Gb/s), Gen5 (32Gb/s), and is fully compliant with PCI Express Base Specification, Revision 5.0.

Highlights
Features
Standard Deliverables
Example Applications

PCIe5 fully covers all major processes, such as 14nm, 12nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm
PCIe4/3/2 fully covers all major processes, such as 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm
Offers leading performance, power, and area per terabit
Optional Pl/Sl and thermal co-design service
Full support from IP delivery to production

Reference Clock

25-300MHz, integer multiple of Serial output
+/-300ppm frequency stability (<20Gbps)
+/-100ppm frequency stability (>=20Gbps)
Supports both SRNS & SRIS modes
Configurable as reference clock repeater

Internal PLL

Used to drive all PHY transmitters and receivers
LC-tank architecture operational from 16-32 Gbps
Ring PLL covering 1.0-16Gbps
Programmable pre-divider & feedback divider
Initiative SSC or reference clock based passive SSC
LOCK indication

Data Transmit

Rates supported from 1.0-32 Gbps
AC coupled
50Ω impedance, internally calibrated
200-1100mV differential peak-peak, programmable

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for Sl evaluation
Integration Guidelines
Test Guidelines
GDSIl Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

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