PCIe 5.0/4.0/3.0 - INNOSILICON

PCIe 5.0/4.0/3.0 PHY & Controller

Innosilicon’s PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specifications. These solutions deliver exceptional performance, low latency, power efficiency, and unparalleled flexibility, making them ideal for enterprise computing, storage networks, automotive, and I/O connectivity applications.

PCIe 5.0/4.0/3.0 PHY & Controller

The Innosilicon PCIe 5.0/4.0/3.0 PHY is a highly configurable IP supporting data rates of up to 32Gbps per lane. It features NRZ signaling for 2.5, 5.0, 8.0, 16.0, and 32GT/s. The PHY seamlessly interoperates with Innosilicon’s PCIe 5.0 controller, ensuring robust performance and compatibility.

The Innosilicon Gen5 PCI Express Controller supports both Root Complex (RC) and Endpoint (EP) applications. It is a high-performance, high-reliability solution with low latency, minimal area, and power efficiency. The controller supports up to x8 lanes across all generations, fully compliant with the PCI Express Base Specification, Revision 5.0.

Benefits
Features
Deliverables
Applications

PCIe5 fully covers all major processes, such as 14nm, 12nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm
PCIe4/3/2 fully covers all major processes, such as 28nm, 22nm, 14nm, 12nm, 8nm, 7nm, 6nm, 5nm, 4nm, 3nm
Offers leading performance, power, and area per terabit
Optional Pl/Sl and thermal co-design service
Full support from IP delivery to production

Standard PHY interface enables multiple IP sources for PCI Express Logical Layer and provides a target interface for PCI Express PHY vendors.
Supports 2.5/5.0/8.0/16.0Gb/s and 32.0Gb/s serial data transmission rate
Utilizes a 16-bit or 32-bit interface to transmit and receive PCI Express data
Allows integration of high speed components into a single functional block.
Data and clock recovery from serial stream on the PCI Express bus
Holding registers to stage transmit and receive data
Supports direct disparity control for use in transmitting compliance pattern
8b/10b, 128b/130b encode/decode and error indication
Receiver detection
Beacon transmission and reception
Selectable Tx Margining, FFE and signal swing values
Built-In self-test and loopback test
Selectable Tx Margining and FFE taps
Selectable Rx CTLE peaking range and DFE taps
Auto calibrated and tunable on die termination (ODT)
Integrated IO with ESD protection aimed at HBM 2KV and CDM 250V
Well-tuned T-coil to promote ultra-high bandwidth

Verilog Sim Behavioral simulation model for the PHY
Encrypted IO spice netlist for SI evaluation
Integration Guidelines
Test Guidelines
GDSII Layout and layer map for foundry merge
Place and Route LIB and LEF views for the AFE
LVS and DRC verification reports

Enterprise Computing
Storage Networks
Network-on-Chip (NoC)
Automotive
Server Connectivity
GPU Interfacing

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