PCIe6.0/CXL3.0 PHY & Controller
PCIe6.0/CXL3.0 PHY & Controller
The Innosilicon PCle6.x/CXL3.0 PHY is a highly configurable PHY capable of supporting speeds up to 64Gbps within a single lane .The PHY supports NRZ signaling at 2.5,5.0,8.0,16.0,32GT/s, and PAM4 signaling at 64GT/s. The PHY IP can seamlessly interoperate with PCIe6.x controllers and CXL3.0 controllers from Innosilicon. The lnnosilicon Gen6 PCI Express Controller provides a PCI Express Root Complex (RC) and Endpoint (EP) application. It's a high performance, high reliability, low latency, low area, low power, and easy to integrate PCI Express solution. This Controller supports up to x8 Gen1 (2.5Gb/s), Gen2 (5.0Gb/s), Gen3 (8.0Gb/s), Gen4 (16Gb/s), Gen5 (32Gb/s), and Gen6(64Gb/s), fully compliant with PCI Express Base Specifications, Revision 6.0. The Innosilicon CXL3.0 Controller provides three protocols to support accelerators and memory devices. The CXL3.0 shares one PCIe Express electrical layer with PCIe 5.0/6.0, including CXL.io, CXL.cache, and CXL.mem .This Controller is fully compliant with Compute Express Link Specifications, Revision 3.1 .
PCIe6.0/CXL3.0  Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Includes required features in the PCIe Specification 6.0 and CXL Specification Revision 3.0 Version 1
  • High utilization FLIT packing with round-robin access between protocols and fairness between channels in a protocol
  • Low latency
  • Supports for CXL 2.0 68B FLIT, and CXL 3.0 256B FLIT and CXL 3.0 256B latency optimized FLIT operating modes
  • Configurable host or device operation
  • Configurable CXL.cache and/or CXL.mem protocol support
  • Configurable high speed AXI-S style streaming parallel user interfaces for maximum throughput
  • CXL transaction layer implements endpoint address decoding for simple/efficient support of DRAM channels with two configurable levels of decoding to support intra-endpoint and inter-endpoint interleaving schemes
  • Configurable for IDE support for CXL.cachemem in all operating modes
  • 64B / 128B datapath at 1GHz
  • CXL Controller Functional Specification
  • hardware architecture

    interface descriptions

    module descriptions

    register descriptions

    clocking and reset strategy

    configuration guide

  • RTL source code written in Verilog for all modules excluding the IDE modules
  • Encrypted RTL for all IDE-related modules
  • Synthesis and timing constraints and user documentation
  • IP system sanity test bench and user documentation
Use Cases for PCIe6.0/CXL3.0

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