Innosilicon’s low power Fractional-N / SSCG PLL addresses power sensitive designs required for IOT, mobile and other low power applications needing non-integer clock multiplication, programmable clock synthesis, clock tracking or fine tuning on-the-fly, and Spread Spectrum clock generation. The PLL is designed for digital logic processes and use robust design techniques to work in noisy SoC environments, such as high speed communication to low power consumer to memory.
PLL Block Diagram 01
PLL Block Diagram 02
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Low jitter
  • Wide frequency range
  • Small area
  • Dual power supply: 1.8V (analog) & 0.75V(digital) allow for excellent supply noise rejection
  • Input reference clock frequency supports ranging from 10MHz to 500MHz
  • PFD frequency supports ranging from 10MHz to 100MHz
  • VCO frequency supports ranging from 1GHz to 3.2GHz
  • Low jitter
  • Built-in lock detector to indicate the frequency lock state
  • CDL Netlist (MG Calibre Compatible)
  • Functional Verilog Model
  • Liberty timing models (.lib)
  • LEF
  • Application Note
Use Cases for PLL

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