PLL
PLL
Innosilicon’s low-power Fractional-N/SSCG PLL addresses power-sensitive applications. It supports non-integer clock multiplication, programmable clock synthesis, on-the-fly clock tracking or fine tuning, and spread spectrum clock generation. Designed for digital logic processes, the PLL incorporates robust design techniques to operate reliably in noisy SoC environments, such as high-speed communication systems, low power consumer devices, and memory interfaces.
PLL Block Diagram 01
PLL Block Diagram 02
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Low power consumption
  • Low jitter
  • Wide frequency range
  • Small area
  • Supports frequencies from 1GHz to 3.2GHz for versatile applications
  • Low jitter performance
  • Supports Fractional mode to enable fine frequency resolution for precise tuning
  • Supports SSC mode to reduce EMI
  • Supports multiple frequencies and phases
  • Input reference clock frequency is supported ranging from 10MHz to 500MHz
  • Built-in lock detector to indicate the frequency lock state
  • GDSII
  • CDL Netlist (MG Calibre Compatible)
  • Functional Verilog Model
  • Liberty timing models (.lib)
  • LEF
  • Application Note
  • Microprocessors and Microcontrollers
  • FPGAs and ASICs
  • RF Transceivers
  • Serial Data Communication
  • Audio/Video Systems
  • Consumer Electronics
  • Automotive Electronics
  • Radar and Sonar Systems
  • IoT Devices
  • Advanced Driver Assistance Systems
  • Consumer Electronics

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