Power-On-Reset IP
Power-On-Reset IP
Innosilicon POR IP generates a POR signal to reset the digital logic. The POR signal is set low if analog supply or digital supply falls below the threshold voltage, and will be set high if both of analog supply and digital supply exceed the threshold voltage.
POR Block Diagram
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Chip level integration
  • Low power consumption
  • Built-in low-power bandgap reference
  • Supports multiple voltage levels for versatile applications
  • Ensures quick and reliable system initialization
  • Robust against power supply fluctuations and glitches
  • Reliable operation across a wide temperature range
  • Datasheet
  • Physical Integration Guide
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available
  • Microcontrollers & Microprocessors
  • Integrated Circuits
  • Automotive Electronics
  • Industrial Control Systems

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