Power-On-Reset IP
Power-On-Reset IP
Innosilicon POR IP generates a POR signal to reset the digital logic. The POR signal is set low if analog supply or digital supply falls below the threshold voltage, and will be set high if both of analog supply and digital supply exceed the threshold voltage.
POR Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
  • Chip level integration

  • Low power: 12uA current consumption
  • Built-in low power bandgap reference
  • Typical 1.35V threshold for 1.8V IO supply
  • Typical 0.55V threshold for 0.8V core supply
  • The area correlates strongly with process node, please refer to detailed datasheet
  • Datasheet
  • Physical Integration Guide
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available
Use Cases for POR

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