PSRAM/RPC PHY & Controller
PSRAM/RPC
PHY & Controller
The Innosilicon AXI interface PSRAM/RPC Controller (hereinafter referred to as “Controller”) provides four AXI channels to connect to the Innosilicon PSRAM/RPC PHY, which is compliant with the specifications of DFI digital interface.

This Controller takes two-layer architecture which makes the interface flexible and easy to be converted to the desired multi-port bus format and timing sequence. One layer is the CPU bus core with arbitration for a single or a multiport CPU bus; the other layer is the controller core to communicate with the DFI PHY. Between the two layers, a generic command FIFO and TX/RX data FIFO is utilized to make the internal controller immune to the changes of the CPU bus core.

The overall design of the Controller is versatile, light-weight and easily adjustable to the CPU bus ports. It has high efficiency yet not overly large gate counts. All interface timing on DFI and controller is in 1x SDR clock domain which can be half of the speed of the PHY core. The interface is fairly generic and supports high-performance input and output data flow, reaching 400Mbps to 2133Mbps PSRAM speed or 1866Mbps RPC speed in a wide range.
PSRAM/RPC Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
PSRAM:
  • Fully pre-assembled design, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Maintains self-refresh I/O drive state during VDD power down
  • Extensive EDA tool support for various design automation flows
  • DFI compliant memory controller interface
  • Flexible pad ring configuration to adapt for various design and chip scenarios
  • Integration with other Innosilicon interface IP
  • Takes full advantage of process power savings and speed capability
  • Best in class low noise design to ensure best timing margin and signal integrity
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operating modes through simple register interface
  • Per Bit De-skew to improve composite data eye during read cycles at high speed
RPC:
  • Fully compliant with standards
  • Compliant with DFI specification with the clock rate ratio of 1:2 between controller and PHY
  • Controller CPU bus core could be carried on AXI bus interface
  • Supports 4-port switching with respective FIFO set space for each AXI port
  • Automatic initialization and refresh procedure
  • Pipelined design enables high clock rates with minimal routing constraints
  • Run-time configurable timing parameters
  • Supports for RPC device self-refresh and half-sleep mode
  • Source code license available in Verilog HDL
  • Core data path tailored to FPGA family and/or ASIC library
PSRAM:
  • PSRAM modes & signaling, rates from 200Mbps up to 1600Mbps, respectively
  • x8/x16 data path interface
  • 1.8/2.5V I/O devices
  • Multiple drive strengths adjustable
  • Supports read and write timing adjustments with soft calibration
  • Low latency with programmable timings for secure data handling
  • Per bit de-skew support for high speed
  • Supports point to point memory sub systems and multi-rank
  • Supports ZQ calibration to calibrate driver output resistance and on-die termination resistance
  • PVT compensation and timing calibration for all corner reliability
  • At speed BIST, scan insertion
  • Various power-down modes for low power including self-refresh support
  • Low jitter with superior noise rejection
  • APB Port register access interface
  • Supports both wire-bond and flip-chip packaging
  • Wire-bond speed is package limited
RPC:
  • Fully compliant with standards
  • Compliant with DFI specification with the clock rate ratio of 1:2 between controller and PHY
  • Controller CPU bus core could be carried on AXI bus interface
  • Supports 4-port switching with respective FIFO set space for each AXI port
  • Automatic initialization and refresh procedure
  • Pipelined design enables high clock rates with minimal routing constraints
  • Run-time configurable timing parameters
  • Supports for RPC device self-refresh and half-sleep mode
  • Source code license available in Verilog HDL
  • Core data path tailored to FPGA family and/or ASIC library
  • Verilog models
  • LEF
  • Place-and-route abstracts
  • GDSII files
  • LVS netlists
  • Optional extracted HSPICE netlist for I/Os
  • Data book, Application notes
  • Silicon validation and ESD testing results
  • Optional PCB reference design and Package Electrical Model
  • Documentation
  • Documentation for the Innosilicon PHY will be delivered as part of the access package.

  • SDC reference File
  • Simulation environment and user guide
Use Cases for PSRAM/RPC

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