Physical Unclonable ID/Key
Physical Unclonable ID/Key
The Innosilicon PUF IP consists of PUF array and control logic. The PUF array contains 64 to 256 PUF cells and readout circuit. Each PUF cell contains two units with identical physical design. The fabrication process will induce random variation in each unit. The readout circuit is used to compare the difference between the two units and extract a random PUF bit.
PUF Block Diagram
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Easy integrated with pre-assembled hard-macro
  • Fully customizable solutions
  • Root of trust, unclonable, chip dependent ID with unique static and dynamic signature behavior in each chip
  • Process dependent, fully invisible
  • Supports multiple process nodes from 0.18μm to 3nm
  • Small die size
  • Low power consumption
  • PUF size: 64 to 256 bits (could extend to 1K bit)
  • No need for special mask layer, single core voltage supply
  • Large inter-hamming-distance / Small intra-hamming-distance
  • Databook
  • Encrypted Verilog Model
  • Timing Library Model (LIB)
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available
  • Cybersecurity and Data Protection
  • Internet of Things
  • Semiconductor and Electronics Manufacturing
  • Financial Services and Banking

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