10/12-bit SAR ADC
10/12-bit SAR ADC
Innosilicon SAR ADC IP consists of input MUX, ADC core, and digital logic. The input MUX selects the analog signal to be converted from input channels. The ADC core converts the selected analog signal to its digital counterpart. The digital logic controls the ADC operation.
SAR ADC Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    Chip level integration

  • 10/12-bit resolution
  • Up to 5MS/s sampling rate
  • Supports 1~16 single-ended or differential input channels
  • Supports standard I/O cell multiplexed
  • Supports external or internal reference
  • Current consumption: <5mA @ 5MS/s
  • The area correlates strongly with process node and input channel count, please refer to detailed datasheet
  • Databook and detailed physical implementation guides
  • Complete set of timing models
  • Library Exchange Format (LEF)
  • Encrypted Verilog Models
  • Layout vs. Schematic (LVS) report
  • GDSII database
Use Cases for SAR ADC

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