UCIe Chiplet(INNOLINK™)

Innosilicon UCIe Chiplet IP provides a leading-edge chiplet solution allowing massive amounts of low-latency data to pass seamlessly between smaller chips as if they were all on the same bus. Chiplets, defined as independent functional blocks making up a large chip, are pivotal in this new era of heterogeneous integration to achieve performance and efficiency gains. It is a solution as a critical enabler of the power and cost-efficient die-to-die (D2D), chip-to-chip (C2C), board-to-board (B2B), and package-to-package (P2P) connectivity for data centers, networking, 5G, HPC, and AI applications.

Innosilicon UCIe Chiplet IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to a customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, enabling optimized bandwidth up to over 1.5Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.

UCIe-S（Innolink-B） 24Gbps

UCIe-S（Innolink-B） 16Gbps

Highlights
Features
Standard Deliverables
INNOLINK Applications

Supports the latest UCIE 1.1 Version
Flexible Structure, easy to Customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
Supports the CXS/AXI using the streaming package (AXI Interface bandwidth max to 89%)
Supports the CXL/PCIE interface
Fault Tolerant: Support the CRC + Retry + FEC
Supports the FEC Mechanism (Optional)
Low Power: Tunable Driver/Receiver Strength & auto clock gate (Clock Gate Ratio > 95%)
Complete DFX mechanism for Debug
Supports the Performance Monitor (bandwidth width/latency monitor and event monitor)
Supports the Complete BIST & On Die Scope mechanism(Cover protocol layer to the link layer)
Supports the MCM, INFO, and Interposer package plus PCB
High Performance: up to 24Gbps on MCM, 20Gbps on PCB
Auto Tracking: Forward Clock, Support PVT auto tracking
Low Latency: Link layer latency to under 3ns
Full training for the PHY Layer
High Density: Standard Pitch and Micro Bump

Databook and physical implementation guides
Netlist (Spice format for LVS)
Library Exchange Format (LEF)
Verilog Models
GDSII to Foundry IP Merge
Module integration guidelines
WCK/DQ/DV/DX IBIS model with driver and ODT adjustment
Silicon validation report (when available)
Evaluation board (when available)
Data book, Application notes
Verilog Getech File
SDC File
Simulation environment and user guide

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