UCIe Chiplet PHY & Controller
UCIe Chiplet
PHY & Controller
Innosilicon UCIe Chiplet IP is designed to maximize bandwidth between dies / chips / boards / packages, compared to other interfaces available today, at lower power and smaller area budgets. By offering three interconnect options (A/B/C), INNOLINK™ IP can be tailored to customer’s different requirements with an easy-to-use system interface. It is architected for high programmability and flexibility, enabling optimized bandwidth up to over 1.5Tbps while maintaining signal integrity and low latency. Adopting the INNOLINK™ IP in your system will definitely benefit high performance computing ASICs/FPGAs, such as CPU, GPU, AI accelerator, and much more.
UCIe-S(Innolink-B) 24Gbps Eye Diagram
UCIe-S(Innolink-B) 24Gbps
UCIe-S(Innolink-B) 16Gbps Eye Diagram
UCIe-S(Innolink-B) 16Gbps
  • Highlights
  • Features
  • Standard Deliverables
  • INNOLINK Applications
Three Types of UCIe Chiplet
  • Support the latest UCIE 1.1 Version
  • Flexible Structure easy to Customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
  • Support the CXS/AXI using the streaming package (AXI Interface bandwidth max to 89%)
  • Support the CXL/PCIE interface
  • Fault Tolerant: Support the CRC + Retry + FEC
  • Support the FEC Mechanism (Optional)
  • Low Power: Tunable Driver/Receiver Strength & auto clock gate (Clock Gate Ratio > 95%)
  • Complete DFX mechanism for Debug
  • Support the Performance Monitor (bandwidth width/latency monitor and event monitor)
  • Support the Complete BIST & On Die Scope mechanism(Cover the protocol later to the link layer)
  • Support the MCM, INFO and Interposer package plus PCB
  • High Performance: up to 24Gbps on MCM,20Gbps on PCB
  • Auto Tracking: Forward Clock, Support PVT auto tracking
  • Low Latency: Link layer latency to under 3ns
  • full training for the PHY Layer
  • High Density: Standard Pitch and Micro Bump
  • Databook and physical implementation guides
  • Netlist (Spice format for LVS)
  • Library Exchange Format (LEF)
  • Verilog Models
  • GDSII to Foundry IP Merge
  • Module integration guidelines
  • WCK/DQ/DV/DX IBIS model with driver and ODT adjustment
  • Silicon validation report (when available)
  • Evaluation board (when available)
  • Data book, Application notes
  • Verilog Getech File
  • SDC File
  • Simulation environment and user guide
Ucie Chiplet Connection Scene

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