USB 2.0/HSIC PHY(Host/Device/OTG/Hub)/
The Innosilicon USB 2.0 PHY conforms to the specification of UTMI+ level 3 Revision 1.0 (USB 2.0 Transceiver Macrocell Interface Plus) and has excellent performance. As an integrated high-speed mixed signal circuit, the Innosilicon USB 2.0 PHY supports not only the Low Speed (LS) traffic at 1.5Mbps and Full Speed (FS) traffic at 12Mbps, but also the High Speed (HS) traffic at 480Mbps, while retaining backward compatibility with USB1.1 legacy protocol.

The Innosilicon USB 2.0 PHY is capable to handle the low-level protocol and signaling. In transmitting mode, the PHY serializes data, performs bit stuffing following NRZI encoding when needed, and then generates SYNC and EOP fields. Likewise, in receiving mode, it recovers clock from incoming data, strips the SYNC and EOP fields, performs NRZI decoding with bit un-stuffing when needed and then de-serializes the data. It supports17 modes of operations, including LS, FS, HS, On-The-Go (OTG), and Device and Host.

The Innosilicon USB 2.0 PHY can be pre-configured as a 30MHz 16-bit or 60MHz 8-bit UTMI data interface, which provides a complete on-chip transceiver physical solution with ESD protection.

The eUSB2 IP supports native mode and repeater mode, to make the application more flexible. The eUSB2 repeater converts between standard USB 2.0 and eUSB2 signaling levels, allowing legacy USB 2.0 devices to connect to a system-on-chip (SoC) with eUSB2 PHY. Building on years of customer successes with our silicon-proven USB PHY product line , Innosilicon provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-IF) eUSB2 and USB 2.0 specifications.
USB2.0 Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • power consumption
  • Fully customizable
  • High speed hub use VLPI low latency
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Compliant with USB Specification Revision 2.0, 1.1
  • Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
  • Compliant with OTG Supplement to the USB Specification Revision 2.0(Optional)
  • Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
  • Supports low latency hub mode with 40-bit time round trip delay
  • Supports all test modes as defined in the USB Specification Revision2.0
  • Supports scan and loop-back BIST mode
  • Built-in I/O and ESD structure
  • On-die self-calibrated HS/FS/LS termination
  • Supports 12/19.2/20/24MHz (as long as the value is an aliquot part of 480) external crystal or on-chip reference clock with integrated phase-locked loop (PLL) oscillator
  • Embedded ESD circuit with HBM of 2000V and CDM of 500V
  • Databook and detailed physical implementation guides for the complete PHY
  • Library Exchange Format (LEF) file with pin size and locations
  • Gate-level netlist and Standard Delay Format (SDF) Timing file
  • Encrypted Verilog Models
  • Layout Versus Schematic (LVS) flattened netlist and report
  • Design Rule Check (DRC) report
  • GDSII database for foundry merge
  • Optional Test-chip and FPGA support
  • Optional backend integration
Use Cases for USB2.0

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