USB2.0 PHY(HSIC/Host/Device/OTG/Hub)/
eUSB PHY
USB2.0 PHY
(Host/Device/OTG/Hub)/
eUSB PHY
The Innosilicon USB 2.0 IP is capable of handling the low-level protocol and signaling. In transmitting mode, the PHY serializes data, performs bit stuffing following NRZI encoding when needed, and then generates SYNC and EOP fields. Likewise, in receiving mode, it recovers clock from incoming data, strips the SYNC and EOP fields, performs NRZI decoding with bit un-stuffing when needed and then de-serializes the data. It supports 17 modes of operations, including LS, FS, HS, On-The-Go, Device , Host and HSIC.

The Innosilicon eUSB 2.0 IP supports both native and repeater mode. In the native mode, it is intended for board-level chip-to-chip communication. In the repeater mode, it supports standard USB 2.0 communication through a separate eUSB 2.0 repeater component.
USB2.0 Block Diagram
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Fully pre-assemble, Drop-in hard macro to ease integration and speed time to market
  • Zero risk with robust ESD architecture
  • Extensive EDA tool support for various design automation flows
  • DFT functions to reduce test time and ensure high test coverage
  • Several programmable PHY operation modes through simple register interface
  • Compliant with USB Specification Revision 2.0, 1.1
  • Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
  • Compliant with OTG Supplement and High-Speed-Inter-Chip (HSIC) USB supplement to the USB Specification Revision 2.0
  • Compliant with eUSB specification
  • Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
  • Supports low latency hub mode with 40-bit time round trip delay
  • Supports all test modes as defined in the USB Specification Revision 2.0
  • Supports scan and loop-back BIST mode
  • Built-in I/O and ESD structure
  • On-die self-calibrated HS/FS/LS termination
  • Supports 12/19.2/20/24MHz (as long as the value is an aliquot part of 480) external crystal or on-chip reference clock with integrated phase-locked loop (PLL) oscillator
  • Databook and detailed physical implementation guides for the complete PHY
  • Library Exchange Format (LEF) file with pin size and locations
  • Gate-level netlist and Standard Delay Format (SDF) Timing file
  • Encrypted Verilog Models
  • Layout Versus Schematic (LVS) flattened netlist and report
  • Design Rule Check (DRC) report
  • GDSII database for foundry merge
  • Optional Test-chip and FPGA support
  • Optional backend integration
  • Consumer Electronics
  • Industrial Applications
  • Medical Devices
  • Automotive Systems
  • Computing and IT Infrastructure

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