INNOSILICON™ HBM4/3E IP is fully compliant with the JEDEC standard for HBM3E and the preliminary specification for HBM4. The IP includes a customizable controller and PHY. It supports 256-bit memory access per channel, with a 1024-bit input/output interface for HBM3E and up to a 2048-bit interface for HBM4. Similar to previous generations, HBM4/3E supports two, four, eight, twelve, or sixteen DRAM stacks on a base die. HBM3E provides a memory capacity of up to 48 GB, and a data rate of up to 9.6 Gbps per pin.
INNOSILICON™ IP offering also includes full GDS delivery, signal integrity and power integrity (SI/PI) analysis, verification models, prototyping support, and simulation tools. These offerings empower customers to accelerate development cycles, ensure robust performance, and reliability.
