INNOSILICON™ introduces its UALink PHY and Controller IP, purpose-built for the AI era’s high-performance chip design needs. This solution is fully compliant with UALink Common Specification Rev2.0 standards.
The UALink IP integrates high-performance interconnect 112G/224G SerDes. Fine-grained configuration and strong adaptability deliver stable link transmission in scale-up network and power efficiency under variable traffic, temperature and voltage conditions, satisfying strict long-term silicon operating requirements.
The UALink IP supports 800Gbps and 400Gbps bandwidth modes with backward compatibility for 200Gbps and 100Gbps. It serves as an ideal interconnect solution for devices demanding ultra-high bandwidth, ultra-low latency and super-node architectures. Typical application scenarios include large-scale AI training, HPC, edge-side AI inference, and switching devices.
Leveraging the synergy of “core IP + complete solution”, INNOSILICON™ UALink one-stop IP solution supports advanced cutting-edge process nodes, helping customers mitigate the technical risks of developing UALink interconnect IP. It shortens integration cycles for high-speed inter-chip interfaces in high-performance computing chips and empowers customers to gain a competitive edge in next-generation ultra-low-latency high-bandwidth interconnection solutions.
