DP1.4/eDP1.4 TX & RX PHY and Controller
DP1.4/eDP1.4
TX & RX PHY and Controller
Innosilicon eDP/DP TX IP is used to transmit video, audio, and auxiliary data from video source device to display device. It contains the digital controller and the physical layer. The digital controller processes the input video and audio data and outputs encoded data to the physical layer. The physical layer contains the main link, the AUX channel, PLL, and bias circuit, which converts the parallel data to serial stream.

Innosilicon eDP/DP RX IP is used to receive and recover video and audio data from the DP/eDP source device. It also contains the physical layer and the digital controller. The physical layer converts the received serial stream to digital parallel data and output to the digital controller. The digital controller decodes the parallel data and recovers the video and audio information.

The AUX channel employs a half-duplex bidirectional link to transmit and receive auxiliary information, such as EDID information and link status, between a transmitter and a receiver device. PLL generates the clocks required by data channels and the digital logic. The bias circuit generates voltage and current reference.
DP/eDP Block Diagram
  • Highlights
  • Features
  • Standard Deliverables
  • Example Applications
  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Compliant with DP1.4 and eDP1.4 specifications
  • Supports 1/2/4-lane configuration
  • Supports data rate up to 8.1Gbps (HBR3) per data lane
  • Supports RGB and YCbCr444/422/420 video format with 6/8/10/12/16-bit color depth
  • Supports 8-ch I2S and 2-ch S/PDIF audio interface with sampling rate up to 192KHz
  • Supports AUX channel working in 1MHz Manchester-II coding mode
  • Supports programmable termination and equalization
  • Supports HDCP1.4/2.2 (optional)
  • Supports DSC1.2 (optional)
  • Supports SSC modulation
  • Supports BIST and Loopback
  • APB slave interface for internal register access
  • Built-in low jitter core PLL, bandgap reference, and optional pixel PLL
  • The area and power consumption correlate strongly with process node and data lane count, please refer to detailed datasheet
  • For USB Type-C application, please refer to the detailed datasheet
  • Datasheet
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available
Use Cases for DP/eDP

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