DP1.4/eDP1.4 TX & RX PHY and Controller
DP1.4/eDP1.4
TX & RX PHY and Controller
Innosilicon eDP/DP TX IP transmits video, audio, and auxiliary data from a video source device to a display device. It consists of a digital controller and a physical layer. The digital controller processes the input video and audio data and outputs encoded data to the physical layer. The physical layer includes the main link, the AUX channel, a PLL, and a bias circuit, which convert the parallel data to a serial stream.

Innosilicon eDP/DP RX IP receives and recovers video and audio data from a DP/eDP source device. It also comprises a physical layer and a digital controller. The physical layer converts the received serial stream to parallel data and outputs it to the digital controller. The digital controller decodes the parallel data and recovers the video and audio information.
  • Benefits
  • Features
  • Deliverables
  • Applications
  • Low power consumption
  • Fully customizable
  • Small area
  • Simple integration process
  • Available options include
  • Test chips and test boards

    FPGA integration support

    Chip level integration

  • Compliant with DP1.4 and eDP1.4 specifications
  • Supports 1/2/4-lane configuration
  • Supports data rate up to 8.1Gbps (HBR3) per data lane
  • Supports RGB and YCbCr444/422/420 video formats with 6/8/10/12/16-bit color depth
  • Supports 8-ch I2S and 2-ch S/PDIF audio interface with sampling rate up to 192KHz
  • Supports AUX channel working in 1MHz Manchester-II coding mode
  • Supports programmable termination and equalization
  • Supports HDCP1.4/2.2 (optional)
  • Supports DSC1.2 (optional)
  • Supports SSC modulation
  • Supports BIST and Loopback
  • APB slave interface for internal register access
  • Built-in low jitter core PLL, bandgap reference, and optional pixel PLL
  • The area and power consumption correlate strongly with process node and data lane count, and please refer to detailed datasheet
  • For USB Type-C application, please refer to the detailed datasheet
  • Datasheet
  • Physical Integration Guide
  • Timing Library Model (LIB)
  • Encrypted Verilog Model
  • Library Exchange Format (LEF)
  • GDSII Database
  • Evaluation Board if Available
Use Cases for DP/eDP

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